Invention Grant
US09412462B2 3D stacked memory array and method for determining threshold voltages of string selection transistors
有权
3D堆叠存储器阵列和用于确定串选择晶体管的阈值电压的方法
- Patent Title: 3D stacked memory array and method for determining threshold voltages of string selection transistors
- Patent Title (中): 3D堆叠存储器阵列和用于确定串选择晶体管的阈值电压的方法
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Application No.: US14798561Application Date: 2015-07-14
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Publication No.: US09412462B2Publication Date: 2016-08-09
- Inventor: Byung-Gook Park , Sang-Ho Lee
- Applicant: Seoul National University R&DB FOUNDATION
- Applicant Address: KR
- Assignee: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
- Current Assignee: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
- Current Assignee Address: KR
- Agent Gerald E. Hespos; Michael J. Porco; Matthew T. Hespos
- Priority: KR10-2014-0089558 20140716
- Main IPC: G11C16/04
- IPC: G11C16/04 ; G11C16/34 ; H01L27/115

Abstract:
This invention provides 3D stacked memory arrays and methods for determining threshold voltages of string selection transistors by LSMP (layer selection by multi-level permutation) for enabling to select layers regardless of the number or as many as possible by the limited numbers of threshold voltage states and SSLs. Thus, this invention enables to maximize the degree of integrity of memory by minimizing the number of SSLs and to select layers with no limitation of the number by considering a recent aspect ratio of the semiconductor etching process.
Public/Granted literature
- US20160019973A1 3D STACKED MEMORY ARRAY AND METHOD FOR DETERMINING THRESHOLD VOLTAGES OF STRING SELECTION TRANSISTORS Public/Granted day:2016-01-21
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