Invention Grant
US09412462B2 3D stacked memory array and method for determining threshold voltages of string selection transistors 有权
3D堆叠存储器阵列和用于确定串选择晶体管的阈值电压的方法

3D stacked memory array and method for determining threshold voltages of string selection transistors
Abstract:
This invention provides 3D stacked memory arrays and methods for determining threshold voltages of string selection transistors by LSMP (layer selection by multi-level permutation) for enabling to select layers regardless of the number or as many as possible by the limited numbers of threshold voltage states and SSLs. Thus, this invention enables to maximize the degree of integrity of memory by minimizing the number of SSLs and to select layers with no limitation of the number by considering a recent aspect ratio of the semiconductor etching process.
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