Invention Grant
- Patent Title: Three-dimensional integrated circuit device fabrication including wafer scale membrane
- Patent Title (中): 三维集成电路器件制造包括晶圆膜
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Application No.: US14597327Application Date: 2015-01-15
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Publication No.: US09412620B2Publication Date: 2016-08-09
- Inventor: Douglas C. La Tulipe, Jr. , Sampath Purushothaman , James Vichiconti
- Applicant: GlobalFoundries U.S. 2 LLC
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agent Yuanmin Cai, Esq.
- Main IPC: H01L21/77
- IPC: H01L21/77 ; H01L21/322 ; H01L21/02 ; H01L21/683 ; H01L21/762 ; H01L23/00 ; H01L25/065 ; H01L25/00 ; H01L29/06 ; C23C16/40 ; C23C16/513 ; C23C16/56 ; H01L21/18 ; H01L21/67
Abstract:
Method and Apparatus so configured for the fabrication of three-dimensional integrated devices. A crystalline substrate within an area of a donor semiconductor wafer is etched. The substrate side is located opposite a device layer and has a buried insulating layer and a substrate thickness. The etching removes at least a substantial portion of the crystalline substrate within the area such that the device layer and the buried insulating layer in the area is to conform to a pattern specific topology on an acceptor surface. The donor semiconductor wafer is supported with a supporting structure that allows the donor semiconductor wafer to flexibly conform to the pattern specific topology within at least a portion of the area after the etching to enable conformality and reliable bonding to the device surfaces of an acceptor wafer to form a three dimensional integrated device.
Public/Granted literature
- US20150147869A1 THREE-DIMENSIONAL INTEGRATED CIRCUIT DEVICE FABRICATION INCLUDING WAFER SCALE MEMBRANE Public/Granted day:2015-05-28
Information query
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