A method for fabricating semiconductor devices, including: providing a CMOS fabric and metal layers, the metal layers including a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer, the metal layers providing interconnection for the CMOS fabric, and constructing mask defined connections between the third metal layer and the fourth metal layer, the mask defined connections are substantially similar to antifuse programmed connections of a programmed antifuse programmable device, where the antifuse programmable device is a 3D antifuse programmable device including antifuses and antifuse programming transistors, where the antifuse programming transistors overlay the antifuses, and where the antifuse programming transistors include a monocrystalline channel.