Invention Grant
- Patent Title: Via definition scheme
- Patent Title (中): 通过定义方案
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Application No.: US14024103Application Date: 2013-09-11
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Publication No.: US09412647B2Publication Date: 2016-08-09
- Inventor: Yen-Cheng Lu , Chih-Tsung Shih , Shinn-Sheng Yu , Jeng-Horng Chen , Anthony Yen
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/76
- IPC: H01L21/76 ; H01L23/52 ; H01L21/768 ; H01L21/033 ; H01L21/311

Abstract:
A method includes defining a metal pattern layer over a first dielectric layer. The first dielectric layer is disposed over an etch stop layer and the etch stop layer is disposed over a second dielectric layer. A spacer layer is grown over the metal pattern layer and the first dielectric layer. A metal trench is formed with a metal width in the first dielectric layer. A via hole is formed with a via width in the second dielectric layer.
Public/Granted literature
- US20150069622A1 Via Definition Scheme Public/Granted day:2015-03-12
Information query
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