Invention Grant
- Patent Title: Method of manufacturing semiconductor package
- Patent Title (中): 制造半导体封装的方法
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Application No.: US14702662Application Date: 2015-05-01
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Publication No.: US09412707B2Publication Date: 2016-08-09
- Inventor: Hyun-soo Chung , Tae-je Cho , Jung-seok Ahn , In-young Lee
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR
- Agency: Renaissance IP Law Group LLP
- Priority: KR10-2014-0072974 20140616
- Main IPC: H01L29/40
- IPC: H01L29/40 ; H01L23/00 ; H01L23/48 ; H01L21/78 ; H01L21/304 ; H01L21/683 ; H01L25/00 ; H01L25/065 ; H01L21/768 ; H01L21/48 ; H01L23/31 ; H01L21/56

Abstract:
Embodiments of the inventive aspect include a method of manufacturing a semiconductor package including a plurality of stacked semiconductor chips in which edges of a semiconductor wafer substrate may be prevented from being damaged or cracked when the semiconductor package is manufactured at a wafer level, while a diameter of a molding element is greater than a diameter of the semiconductor wafer substrate. The molding element may cover a surface of the wafer substrate and the plurality of stacked semiconductor chips. Embodiments may include a wafer level semiconductor package including a circular substrate having a first diameter, a circular passivation layer attached to the circular substrate, the passivation layer having the first diameter, and a circular molding element covering surfaces of the plurality of semiconductor chips, and covering an active area of the substrate. The circular molding element may have a second diameter that is greater than the first diameter.
Public/Granted literature
- US20150364432A1 METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE Public/Granted day:2015-12-17
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