Invention Grant
- Patent Title: 3DIC interconnect apparatus and method
- Patent Title (中): 3DIC互连设备和方法
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Application No.: US14135103Application Date: 2013-12-19
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Publication No.: US09412719B2Publication Date: 2016-08-09
- Inventor: Shu-Ting Tsai , Dun-Nian Yaung , Jen-Cheng Liu , U-Ting Chen , Shih Pei Chou
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L25/065 ; H01L25/00 ; H01L23/00 ; H01L21/768
Abstract:
An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls of the first opening. One or more etch processes form one or more spacer-shaped structures along sidewalls of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.
Public/Granted literature
- US20150179612A1 3DIC Interconnect Apparatus and Method Public/Granted day:2015-06-25
Information query
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