Invention Grant
US09412728B2 Post-CMOS processing and 3D integration based on dry-film lithography
有权
基于干膜光刻的后CMOS处理和3D集成
- Patent Title: Post-CMOS processing and 3D integration based on dry-film lithography
- Patent Title (中): 基于干膜光刻的后CMOS处理和3D集成
-
Application No.: US14418842Application Date: 2013-07-19
-
Publication No.: US09412728B2Publication Date: 2016-08-09
- Inventor: Carlotta Guiducci , Yusuf Leblebici , Yuksel Temiz
- Applicant: ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)
- Applicant Address: CH
- Assignee: ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)
- Current Assignee: ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)
- Current Assignee Address: CH
- Agency: Sheridan Ross P.C.
- Priority: EP12179308 20120803
- International Application: PCT/IB2013/055946 WO 20130719
- International Announcement: WO2014/020479 WO 20140206
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L25/00 ; H01L21/768 ; H01L23/00 ; G03F7/20 ; G03F7/32
Abstract:
A method for performing a post processing pattern on a diced chip having a footprint, comprises the steps of providing a support wafer; applying a first dry film photoresist to the support wafer; positioning a mask corresponding to the footprint of the diced chip on the first dry film photoresist; expose the mask and the first dry film photoresist to UV radiation; remove the mask; photoresist develop the exposed first dry film photoresist to obtain a cavity corresponding to the diced chip; positioning the diced chip inside the cavity; applying a second dry film photoresist to the first film photoresist and the diced chip; and expose and develop the second dry film photoresist applied to the diced chip in accordance with the post processing pattern.
Public/Granted literature
- US20150371978A1 POST-CMOS PROCESSING AND 3D INTEGRATION BASED ON DRY-FILM LITHOGRAPHY Public/Granted day:2015-12-24
Information query
IPC分类:
