Invention Grant
- Patent Title: CMOS gate contact resistance reduction
- Patent Title (中): CMOS栅极接触电阻降低
-
Application No.: US14566779Application Date: 2014-12-11
-
Publication No.: US09412759B2Publication Date: 2016-08-09
- Inventor: Anthony I. Chou , Arvind Kumar , Sungjae Lee
- Applicant: GLOBALFOUNDRIES INC.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Main IPC: H01L27/12
- IPC: H01L27/12 ; H01L29/06 ; H01L29/423 ; H01L29/66 ; H01L21/311 ; H01L21/84 ; H01L21/28

Abstract:
A gate contact with reduced contact resistance is provided by increasing contact area between the gate contact and a gate conductive portion of a gate structure. The gate contact forms a direct contact with a topmost surface and at least portions of outermost sidewalls of a portion of the gate conductive portion, thus increasing the contact area between the gate contact and the gate structure. The gate contact area of the present application can be further increased by completely surrounding a portion of the gate conductive portion of the gate structure with the gate contact.
Public/Granted literature
- US20160172378A1 CMOS GATE CONTACT RESISTANCE REDUCTION Public/Granted day:2016-06-16
Information query
IPC分类: