Invention Grant
US09412871B2 FinFET with channel backside passivation layer device and method
有权
具有沟道背面钝化层的FinFET器件及方法
- Patent Title: FinFET with channel backside passivation layer device and method
- Patent Title (中): 具有沟道背面钝化层的FinFET器件及方法
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Application No.: US13791325Application Date: 2013-03-08
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Publication No.: US09412871B2Publication Date: 2016-08-09
- Inventor: Gerben Doornbos , Mark van Dal , Georgios Vellianitis , Blandine Duriez , Krishna Kumar Bhuwalka , Richard Kenneth Oxland , Martin Christopher Holland , Yee-Chaung See , Matthias Passlack
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/66 ; H01L29/10

Abstract:
A FinFET with backside passivation layer comprises a template layer disposed on a substrate, a buffer layer disposed over the template layer, a channel backside passivation layer disposed over the buffer layer and a channel layer disposed over the channel backside passivation layer. A gate insulator layer is disposed over and in contact with the channel layer and the channel backside passivation layer. The buffer layer optionally comprises aluminum and the channel layer may optionally comprise a III-V semiconductor compound. STIs may be disposed on opposite sides of the channel backside passivation layer, and the channel backside passivation layer may have a top surface disposed above the top surface of the STIs and a bottom surface disposed below the top surface of the STIs.
Public/Granted literature
- US20140252478A1 FinFET with Channel Backside Passivation Layer Device and Method Public/Granted day:2014-09-11
Information query
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