System and methods are provided for signal processing. For example, an input signal is received at a finite impulse response filter circuit including a plurality of stages, where each stage of the plurality of stages is associated with a sample value of the input signal and a stage weight. An output signal is generated using the finite impulse response filter circuit, the output signal being equal to a weighted sum of the sample values of the input signal. An error signal is generated to indicate a difference between the output signal and a target. A constraint is applied to one or more of the stage weights. The stage weights are changed within the constraint to reduce a magnitude of the error signal.