Invention Grant
US09417282B2 Method for managing the operation of a circuit with triple modular redundancy and associated device
有权
用于管理具有三重模块冗余和相关设备的电路的操作的方法
- Patent Title: Method for managing the operation of a circuit with triple modular redundancy and associated device
- Patent Title (中): 用于管理具有三重模块冗余和相关设备的电路的操作的方法
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Application No.: US14662530Application Date: 2015-03-19
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Publication No.: US09417282B2Publication Date: 2016-08-16
- Inventor: Jean-Marc Daveau , Sylvain Clerc , Philippe Roche
- Applicant: STMICROELECTRONICS (CROLLES 2) SAS
- Applicant Address: FR Crolles
- Assignee: STMICROELECTRONICS (CROLLES 2) SAS
- Current Assignee: STMICROELECTRONICS (CROLLES 2) SAS
- Current Assignee Address: FR Crolles
- Agency: Allen, Dyer, Doppelt, Milbrath & Gilchrist, P.A.
- Priority: FR1456023 20140627
- Main IPC: G06F11/08
- IPC: G06F11/08 ; G01R31/3177 ; G06F11/267 ; G01R31/3185 ; G06F11/18

Abstract:
A method for managing operation of a logic component is provided, with the logic component including a majority vote circuit and an odd number of flip-flops equal to at least three. The method includes, following a normal operating mode of the logic component, placing a flip-flop in a test mode, and injecting a test signal into a test input of the flip-flop being tested while a logic state of the other flip-flops is frozen. A test signal output is analyzed. At the end of the test, the logic component is placed back in the normal operating mode. The majority vote circuit restores a value of the output signal from the logic component that existed prior to initiation of the test.
Public/Granted literature
- US20150377962A1 METHOD FOR MANAGING THE OPERATION OF A CIRCUIT WITH TRIPLE MODULAR REDUNDANCY AND ASSOCIATED DEVICE Public/Granted day:2015-12-31
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