Invention Grant
- Patent Title: Method of manufacturing a semiconductor device and semiconductor integrated circuit wafer
- Patent Title (中): 制造半导体器件和半导体集成电路晶片的方法
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Application No.: US14317648Application Date: 2014-06-27
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Publication No.: US09431321B2Publication Date: 2016-08-30
- Inventor: Shinya Watanabe , Kazuyuki Higashi , Taku Kamoto
- Applicant: KABUSHIKI KAISHA TOSHIBA
- Applicant Address: JP Tokyo
- Assignee: KABUSHIKI KAISHA TOSHIBA
- Current Assignee: KABUSHIKI KAISHA TOSHIBA
- Current Assignee Address: JP Tokyo
- Agency: Holtz, Holtz & Volek PC
- Priority: JP2014-052071 20140314
- Main IPC: H01L23/544
- IPC: H01L23/544 ; H01L23/48 ; H01L21/768 ; H01L23/538 ; H01L21/82 ; H01L21/683 ; H01L21/66 ; H01L23/00

Abstract:
According to one embodiment, a method of manufacturing a semiconductor device comprises forming through holes extending through a semiconductor substrate in a thickness direction to integrated circuits in chip areas, and forming a first mark opening and second mark openings in a dicing line. The method detects the first mark opening based on positions of the second mark openings. Then, the method performs alignment of exposure positions based on the position of the first mark opening to perform photolithography, thereby forming a resist pattern on the back side of the semiconductor substrate.
Public/Granted literature
- US20150255373A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT WAFER Public/Granted day:2015-09-10
Information query
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