An electronic device comprising a clock unit and a processing unit connected to the clock unit is described. The clock unit may deliver an output clock signal for operating the processing unit in accordance with the output clock signal. The clock unit may have: a normal mode in which the output clock signal has a low amount of jitter and a normal clock rate to enable normal use of the electronic device, and a failure analysis mode in which the output clock signal has a high amount of jitter or a reduced clock rate, or a high amount of jitter combined with a reduced clock rate, to impede the normal use. The clock unit may be protected against unauthorized re-activation of the normal mode. A method of protecting an electronic device against unauthorized use is also described.