Invention Grant
- Patent Title: Processor interrupt interface with interrupt partitioning and virtualization enhancements
- Patent Title (中): 处理器中断接口具有中断分区和虚拟化增强功能
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Application No.: US13570874Application Date: 2012-08-09
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Publication No.: US09436626B2Publication Date: 2016-09-06
- Inventor: Bryan D. Marietta , Gary L. Whisenhunt , Kumar K. Gala , David B. Kramer
- Applicant: Bryan D. Marietta , Gary L. Whisenhunt , Kumar K. Gala , David B. Kramer
- Applicant Address: US TX Austin
- Assignee: FREESCALE SEMICONDUCTOR, INC.
- Current Assignee: FREESCALE SEMICONDUCTOR, INC.
- Current Assignee Address: US TX Austin
- Main IPC: G06F13/26
- IPC: G06F13/26 ; G06F9/50 ; G06F9/45 ; G06F13/14 ; G06F13/24 ; G06F9/455
Abstract:
A method and circuit for a data processing system (200) provide a processor-based partitioned priority blocking mechanism by storing interrupt identifiers, partition identifiers, thread identifiers, and priority levels associated with accepted interrupt requests in special purpose registers (35-38) located at the processor core (26) to enable quick and efficient interrupt priority blocking on a partition basis.
Public/Granted literature
- US20140047150A1 Processor Interrupt Interface with Interrupt Partitioning and Virtualization Enhancements Public/Granted day:2014-02-13
Information query
