Invention Grant
US09437265B2 Semiconductor device having shallow trench isolation and gate groove
有权
具有浅沟槽隔离和栅极沟槽的半导体器件
- Patent Title: Semiconductor device having shallow trench isolation and gate groove
- Patent Title (中): 具有浅沟槽隔离和栅极沟槽的半导体器件
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Application No.: US14461705Application Date: 2014-08-18
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Publication No.: US09437265B2Publication Date: 2016-09-06
- Inventor: Shinya Iwasa , Migaku Kobayashi
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Priority: JP2013-174288 20130826
- Main IPC: G11C5/06
- IPC: G11C5/06 ; G11C8/14 ; H01L29/423 ; G11C11/408 ; H01L27/02 ; H01L27/108 ; G11C5/02 ; H01L29/417

Abstract:
Semiconductor devices have a substrate including first and second regions of differing conductivity types and a shallow trench isolation isolation region that extends within the first and second regions. First and second active regions are disposed in respective first and second regions, with a gate electrode disposed in a lower portion of a gate groove that extends continuously from the first active region to the second active region, the gate groove being shallower than the shallow trench. A cap insulating film is disposed in an upper portion of the gate groove covering an upper surface of the gate electrode. First and second transistors are within respective first and second active regions and share the gate electrode.
Public/Granted literature
- US20150055394A1 Semiconductor Device Public/Granted day:2015-02-26
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