Invention Grant
US09437475B2 Method for fabricating microelectronic devices with isolation trenches partially formed under active regions
有权
用于制造具有在有源区域部分形成的隔离沟槽的微电子器件的方法
- Patent Title: Method for fabricating microelectronic devices with isolation trenches partially formed under active regions
- Patent Title (中): 用于制造具有在有源区域部分形成的隔离沟槽的微电子器件的方法
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Application No.: US14441354Application Date: 2012-11-08
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Publication No.: US09437475B2Publication Date: 2016-09-06
- Inventor: Maud Vinet , Sylvie Mignot , Romain Wacquez
- Applicant: Commissariat a l'energie atomique et aux energies alternatives
- Applicant Address: FR Paris
- Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
- Current Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
- Current Assignee Address: FR Paris
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- International Application: PCT/US2012/064110 WO 20121108
- International Announcement: WO2014/074096 WO 20140515
- Main IPC: H01L21/762
- IPC: H01L21/762 ; H01L21/84 ; H01L21/311 ; H01L29/06

Abstract:
A method of producing a microelectronic device in a substrate including a first semiconductor layer, a first dielectric layer, and a second semiconductor layer, including: etching a trench through the first semiconductor layer, the first dielectric layer, and a part of the second semiconductor layer, defining one active region, and such that, at the level of the second semiconductor layer, a part of the trench extends under a part of the active region; deposition of one second dielectric layer in the trench; etching the second dielectric layer such that remaining portions of the second dielectric layer forms portions of dielectric material extending under a part of the active region; deposition of a third dielectric layer in the trench such that the trench is filled with the dielectric materials of the second and third dielectric layers and forms an isolation trench.
Public/Granted literature
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