Invention Grant
US09437528B1 Dual-side exposed semiconductor package with ultra-thin die and manufacturing method thereof 有权
具有超薄模的双面裸露半导体封装及其制造方法

Dual-side exposed semiconductor package with ultra-thin die and manufacturing method thereof
Abstract:
A dual-side exposed semiconductor package with ultra-thin die and a manufacturing method are disclosed. A die having a source electrode and a gate electrode at top surface is flipped and attached to a die paddle of a lead frame and then is encapsulated with a first molding compound. The first molding compound and the die are ground to reduce the thickness. A mask is applied atop the lead frame with the back of the flipped die exposed and a metal layer is deposited on the exposed area at the back of the flipped die. A metal clip is attached to the back of the flipped die. A second molding compound is deposited on the lead frame with the top surface of the metal clip exposed from the top surface of the second molding compound and the bottom surface of the lead frame exposed from the bottom surface of the second plastic molding compound.
Information query
Patent Agency Ranking
0/0