Roughly described, a memory device has a multilevel stack of conductive layers which are divided laterally into word lines. Vertically oriented pillars each include series-connected memory cells at cross-points between the pillars and the layers. String select lines run above the conductive layers and define select gates of the pillars. Bit lines run above the SSLs. The pillars are arranged on a regular grid having a unit cell area α, and adjacent ones of the string select lines have respective widths in the bit line direction which are at least as large as (α/pBL). Ground select lines run below the conductive layers and define ground select gates of the pillars. The ground select lines, too, may have respective widths in the bit line direction which are at least as large as (α/pBL).