Invention Grant
US09438215B2 Buffer circuit for buffering and settling input voltage to target voltage level and operation method thereof
有权
用于缓冲和稳定输入电压到目标电压电平的缓冲电路及其操作方法
- Patent Title: Buffer circuit for buffering and settling input voltage to target voltage level and operation method thereof
- Patent Title (中): 用于缓冲和稳定输入电压到目标电压电平的缓冲电路及其操作方法
-
Application No.: US14498623Application Date: 2014-09-26
-
Publication No.: US09438215B2Publication Date: 2016-09-06
- Inventor: Myung-Hwan Lee
- Applicant: SK hynix Inc.
- Applicant Address: KR Gyeonggi-do
- Assignee: SK Hynix Inc.
- Current Assignee: SK Hynix Inc.
- Current Assignee Address: KR Gyeonggi-do
- Agency: IP & T Group LLP
- Priority: KR10-2014-0028317 20140311
- Main IPC: H03K5/02
- IPC: H03K5/02 ; H03K5/24
Abstract:
A buffer circuit includes an amplifying unit suitable for comparing an input voltage of an input terminal with an output voltage of an output terminal, a current sinking unit suitable for controlling a sinking current of the amplifying unit when the input voltage is varied, and a current compensation unit suitable for uniformly maintaining a sinking current amount of the current sinking unit.
Public/Granted literature
- US20150263711A1 BUFFER CIRCUIT AND OPERATION METHOD THEREOF Public/Granted day:2015-09-17
Information query
IPC分类:
