System and methods are provided for processing composite video signals. The system includes: a clock synthesizer configured to generate a line lock clock signal; an interpolation unit configured to generate source data associated with a source composite video signal, the source composite video signal being related to a source clock signal; a buffer unit configured to store the source data based at least in part on the source clock signal and provide destination data based at least in part on the line lock clock signal; a signal processing unit configured to process the destination data to extract a synchronization component and determine a phase error between the synchronization component and the line lock clock signal. The clock synthesizer is further configured to adjust the line lock clock signal based at least in part on the phase error.