A demodulation image sensor, such as used in time of flight (TOF) cameras, extracts all storage- and post-processing-related steps from the pixels to another array of storage and processing elements (proxels) on the chip. The pixel array has the task of photo-detection, first processing and intermediate storage, while the array of storage and processing elements provides further processing and enhanced storage capabilities for each pixel individually. The architecture can be used to address problems due to the down-scaling of the pixel size. Typically, either the photo-sensitivity or the signal storage capacitance suffers significantly. Both a lower sensitivity and smaller storage capacitances have negative influence on the image quality. The disclosed architecture allows for keeping the storage capacitance unaffected by the pixel down-scaling. In addition to that, it provides a high degree of flexibility in integrating more intelligence into the image sensor design already on the level of the pixel array. In particular, if applied to demodulation pixels, the flexibility of the architecture allows for integrating on sensor-level concepts for multi-tap sampling, mismatch compensation, background suppression and so on, without any requirement to adjust the particular demodulation pixel architecture.