A CPU includes a code write unit which writes an interrupt generation code into a page in which the instructions stored in the non-volatile memory are not written, among a plurality of the pages included in an instruction area that is an area of the volatile memory into which the instructions are written, the interrupt generation code being a code for generating a software interrupt, an instruction transfer unit which transfers the instructions from the non-volatile memory to a corresponding page of the volatile memory that is a page in which the interrupt generation code generating the software interrupt is stored when the software interrupt is generated by the interrupt generation code, the instructions being to be stored in the corresponding page, and an instruction execution unit which executes the instructions stored in the instruction area, and when the interrupt generation code is executed, generates a software interrupt.