Invention Grant
- Patent Title: Memory system and assembling method of memory system
- Patent Title (中): 内存系统和内存系统的组装方法
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Application No.: US15001901Application Date: 2016-01-20
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Publication No.: US09443595B2Publication Date: 2016-09-13
- Inventor: Yoshikazu Takeyama , Yuji Nagai
- Applicant: Kabushiki Kaisha Toshiba
- Applicant Address: JP Minato-ku
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2013-232541 20131108
- Main IPC: G11C8/00
- IPC: G11C8/00 ; G11C16/08 ; H01L25/065 ; G11C8/12 ; G11C16/20

Abstract:
According to one embodiment, each memory chip included in a memory package includes a first storage unit that stores therein first information that is n-bit information and is a comparison target of a chip address, and is used for identifying its own memory chip, a second storage unit that stores therein second information for determining an effective bit of the n-bit first information, and a control unit that determines an effective bit of the n-bit first information and an effective bit of the chip address based on the second information.
Public/Granted literature
- US20160141033A1 MEMORY SYSTEM AND ASSEMBLING METHOD OF MEMORY SYSTEM Public/Granted day:2016-05-19
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