Invention Grant
- Patent Title: Connecting techniques for stacked CMOS devices
- Patent Title (中): 堆叠CMOS器件的连接技术
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Application No.: US14102548Application Date: 2013-12-11
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Publication No.: US09443758B2Publication Date: 2016-09-13
- Inventor: Hsiang-Jen Tseng , Wei-Yu Chen , Ting-Wei Chiang , Li-Chun Tien
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Associates, LLC
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L21/768 ; H01L25/065 ; H01L23/528 ; H01L25/00 ; H01L23/48 ; H01L21/822 ; H01L27/06 ; H01L23/535 ; H01L21/74 ; H01L23/522 ; H01L23/532

Abstract:
A stacked integrated circuit includes multiple tiers vertically connecting together. A multi-layer horizontal connecting structure is fabricated inside a substrate of a tier. Layers of the horizontal connecting structure have different patterns as viewed from above the substrate.
Public/Granted literature
- US20150162295A1 CONNECTING TECHNIQUES FOR STACKED CMOS DEVICES Public/Granted day:2015-06-11
Information query
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