Invention Grant
US09443771B1 Methods to thin down RMG sidewall layers for scalability of gate-last planar CMOS and FinFET technology
有权
减薄RMG侧壁层的方法，以实现最终平面CMOS和FinFET技术的可扩展性
- Patent Title: Methods to thin down RMG sidewall layers for scalability of gate-last planar CMOS and FinFET technology
- Patent Title (中): 减薄RMG侧壁层的方法，以实现最终平面CMOS和FinFET技术的可扩展性
-
Application No.: US14935676Application Date: 2015-11-09
-
Publication No.: US09443771B1Publication Date: 2016-09-13
- Inventor: Yanping Shen , Min-hwa Chi , Ashish Kumar Jha , Haiting Wang
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Ditthavong & Steiner, P.C.
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L29/66 ; H01L21/28 ; H01L21/3215 ; H01L21/3213 ; H01L27/092 ; H01L29/49
Abstract:
A method of removing RMG sidewall layers, and the resulting device are provided. Embodiments include forming a TiN layer in nFET and pFET RMG trenches; forming an a-Si layer over the TiN layer; implanting O2 vertically in the a-Si layer; removing the a-Si layer and TiN layer from the side surfaces of the RMG trenches followed by the a-Si layer from the bottom surfaces; forming a TiN layer in the RMG trenches; forming a a-Si layer over the TiN layer; implanting O2 vertically in the a-Si layer; removing the a-Si layer and TiN layer from the side surfaces of the RMG trenches, the a-Si layer from the bottom surfaces, and a remainder of the TiN layer from only the nFET RMG trench; forming a Ti layer in the RMG trenches; implanting Al or C in the Ti layer vertically and annealing; and filling the RMG trenches with Al or W.
Information query
IPC分类:
