Invention Grant
- Patent Title: Top electrode for device structures in interconnect
- Patent Title (中): 互连器件结构的顶部电极
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Application No.: US14880358Application Date: 2015-10-12
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Publication No.: US09444045B2Publication Date: 2016-09-13
- Inventor: Hsia-Wei Chen , Wen-Ting Chu , Kuo-Chi Tu , Chih-Yang Chang , Chin-Chieh Yang , Yu-Wen Liao , Wen-Chun You , Sheng-Hung Shih
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Associates, LLC
- Main IPC: H01L45/00
- IPC: H01L45/00 ; H01L27/24
Abstract:
Some embodiments relate to an integrated circuit device. The integrated circuit device includes a resistive random access memory (RRAM) cell, which includes a top electrode and a bottom electrode that are separated by a RRAM dielectric layer. The top electrode of the RRAM cell has a recess in its upper surface. A via is disposed over the RRAM cell and contacts the top electrode within the recess.
Public/Granted literature
- US20160035975A1 TOP ELECTRODE FOR DEVICE STRUCTURES IN INTERCONNECT Public/Granted day:2016-02-04
Information query
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