Invention Grant
- Patent Title: Double phase-locked loop with frequency stabilization
- Patent Title (中): 具有频率稳定的双锁相环
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Application No.: US14595309Application Date: 2015-01-13
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Publication No.: US09444470B2Publication Date: 2016-09-13
- Inventor: Slobodan Milijevic
- Applicant: MICROSEMI SEMICONDUCTOR ULC
- Applicant Address: CA Kanata, ON
- Assignee: Microsemi Semiconductor ULC
- Current Assignee: Microsemi Semiconductor ULC
- Current Assignee Address: CA Kanata, ON
- Agency: Marks & Clerk
- Agent Richard J. Mitchell
- Main IPC: H03L7/06
- IPC: H03L7/06 ; H03L7/087 ; H03L7/099 ; H03L7/07 ; H03L7/08 ; H03L7/22

Abstract:
A double phase-locked has a first phase-locked loop including a first narrowband loop filter configured to reduce phase noise in a first input clock, and a second phase-locked loop including a second loop filter configured to receive a second input clock from a stable clock source. The second clock has a frequency close to said first clock. The first loop has a bandwidth at least an order of magnitude less than the second loop. A coupler couples the first and second phase-locked loops to provide a common output. The double phase-locked loop can be used, for example, to provide time-of-day information in wireless networks or as a fine filter for cleaning phase noise from clock signals recovered over telecom/datacom networks.
Public/Granted literature
- US20150222276A1 DOUBLE PHASE-LOCKED LOOP WITH FREQUENCY STABILIZATION Public/Granted day:2015-08-06
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