Invention Grant
- Patent Title: Hybrid hidden-line processor and method
- Patent Title (中): 混合隐藏线处理器和方法
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Application No.: US13248071Application Date: 2011-09-29
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Publication No.: US09449118B2Publication Date: 2016-09-20
- Inventor: Gary LaMont Marchant , Shailesh Ratnakar Karmalkar
- Applicant: Gary LaMont Marchant , Shailesh Ratnakar Karmalkar
- Applicant Address: US TX Plano
- Assignee: Siemens Product Lifecycle Management Software Inc.
- Current Assignee: Siemens Product Lifecycle Management Software Inc.
- Current Assignee Address: US TX Plano
- Main IPC: G06T15/40
- IPC: G06T15/40 ; G06F17/50

Abstract:
A method for providing hybrid hidden-line processing for a plurality of polygons representing tessellated image data, wherein each polygon comprises a plurality of edges, is provided. The method includes generating a back-facing plate comprising polygons on a back-facing side of a silhouette of the tessellated image data and a front-facing plate comprising polygons on a front-facing side of the silhouette of the tessellated image data. The method includes tracing the edges and identifying at least one visibility change pixel in each of a subset of the traced edges. The method includes, for each visibility change pixel, determining whether the traced edge is from the same plate as a polygon corresponding to the visibility change pixel. The method includes, for each traced edge that is determined to be from the same plate as the polygon corresponding to the visibility change pixel, displaying the traced edge.
Public/Granted literature
- US20130083022A1 HYBRID HIDDEN-LINE PROCESSOR AND METHOD Public/Granted day:2013-04-04
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