It is proposed a DRAM memory interface (40) for transmitting signals between a memory controller device (50) and a DRAM memory device (52). The DRAM memory interface comprises: data lines (44) for transmitting data signals; one or more control line(s) for transmitting control signals; one or more address line(s) for transmitting address signals; for each line, a transmitter device (41) connected to a first end of the line and a receiver device (42) connected to a second end of the line; wherein: each line is a single ended line wherein a signal transmitted on the line is referenced to a first reference voltage line (46); and—each line has an termination (Z1, Z2) on both the first and second ends of the line by connecting a first impedance (Z1) to the first end of the line and a second impedance (Z2) to the second end of the line.