Invention Grant
US09449707B2 Systems and methods to mitigate program gate disturb in split-gate flash cell arrays
有权
用于减轻分闸门闪存单元阵列中程序门扰动的系统和方法
- Patent Title: Systems and methods to mitigate program gate disturb in split-gate flash cell arrays
- Patent Title (中): 用于减轻分闸门闪存单元阵列中程序门扰动的系统和方法
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Application No.: US14576504Application Date: 2014-12-19
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Publication No.: US09449707B2Publication Date: 2016-09-20
- Inventor: Anirban Roy
- Applicant: FREESCALE SEMICONDUCTOR, INC.
- Applicant Address: US TX Austin
- Assignee: FREESCALE SEMICONDUCTOR, INC.
- Current Assignee: FREESCALE SEMICONDUCTOR, INC.
- Current Assignee Address: US TX Austin
- Main IPC: G11C16/34
- IPC: G11C16/34 ; G11C16/10 ; G11C16/26 ; G11C16/30
Abstract:
A memory circuit has control gate circuitry (104) and select gate circuitry (106). A first memory cell (122/124) has a control gate coupled to the control gate circuitry, a select gate coupled to the select gate circuitry, a drain that is coupled to a first bit line for reading a logic state of the of the first memory cell, and a source. A second memory cell (150/152 or 158/160) having a control gate coupled to the control gate circuitry, a select gate coupled to the select gate circuitry, a drain that is coupled to a second bit line for reading a logic state of the of the second memory cell, and a source. A source control circuit (102) that, during programming of the first memory cell, outputs a first voltage to the source of the first memory cell and keeps the source of the second memory cell floating.
Public/Granted literature
- US20160180954A1 SYSTEMS AND METHODS TO MITIGATE PROGRAM GATE DISTURB IN SPLIT-GATE FLASH CELL ARRAYS Public/Granted day:2016-06-23
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