Invention Grant
- Patent Title: Wafer level package and fabrication method thereof
- Patent Title (中): 晶圆级封装及其制造方法
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Application No.: US14810415Application Date: 2015-07-27
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Publication No.: US09449935B1Publication Date: 2016-09-20
- Inventor: Shing-Yih Shih , Tieh-Chiang Wu
- Applicant: INOTERA MEMORIES, INC.
- Applicant Address: TW Taoyuan
- Assignee: INOTERA MEMORIES, INC.
- Current Assignee: INOTERA MEMORIES, INC.
- Current Assignee Address: TW Taoyuan
- Agent Winston Hsu; Scott Margo
- Main IPC: H01L23/544
- IPC: H01L23/544 ; H01L23/00 ; H01L23/31 ; H01L23/528 ; H01L23/532 ; H01L23/522

Abstract:
A semiconductor device includes a chip having an active surface and a rear surface that is opposite to the active surface; a molding compound covering and encapsulating the chip except for the active surface; and a redistribution layer (RDL) on the active surface and on the molding compound. The RDL is electrically connected to the chip. The RDL includes an organic dielectric layer and an inorganic dielectric hard mask layer on the organic dielectric layer. The RDL further includes metal features in the organic dielectric layer and the inorganic dielectric hard mask layer.
Information query
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