Invention Grant
- Patent Title: Lateral DMOS device with dummy gate
- Patent Title (中): 具有虚拟门的侧面DMOS设备
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Application No.: US13351295Application Date: 2012-01-17
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Publication No.: US09450056B2Publication Date: 2016-09-20
- Inventor: Chun-Wai Ng , Ruey-Hsin Liu , Jun Cai , Hsueh-Liang Chou , Chi-Chih Chen
- Applicant: Chun-Wai Ng , Ruey-Hsin Liu , Jun Cai , Hsueh-Liang Chou , Chi-Chih Chen
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/40 ; H01L29/423 ; H01L29/06
Abstract:
An LDMOS transistor with a dummy gate comprises an extended drift region formed over a substrate, a drain region formed in the extended drift region, a channel region formed in the extended drift region, a source region formed in the channel region and a dielectric layer formed over the extended drift region. The LDMOS transistor with a dummy gate further comprises an active gate formed over the channel region and a dummy gate formed over the extended drift region. The dummy gate helps to reduce the gate charge of the LDMOS transistor while maintaining the breakdown voltage of the LDMOS transistor.
Public/Granted literature
- US20130181285A1 Lateral DMOS Device with Dummy Gate Public/Granted day:2013-07-18
Information query
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