Invention Grant
- Patent Title: Package substrate and manufacturing method thereof
- Patent Title (中): 封装基板及其制造方法
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Application No.: US14685610Application Date: 2015-04-14
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Publication No.: US09458540B2Publication Date: 2016-10-04
- Inventor: Chin-Sheng Wang , Chien-Ming Chen
- Applicant: Subtron Technology Co., Ltd.
- Applicant Address: TW Hsinchu County
- Assignee: Subtron Technology Co., Ltd.
- Current Assignee: Subtron Technology Co., Ltd.
- Current Assignee Address: TW Hsinchu County
- Agency: Jianq Chyun IP Office
- Priority: TW104104529A 20150211
- Main IPC: H01L33/00
- IPC: H01L33/00 ; C23C18/31 ; B32B37/12 ; B32B37/14 ; B65D65/40

Abstract:
A manufacturing method of a package substrate is provided. A first base is formed. Metal bumps are formed on the first base by plating. A second base having an upper and a lower surfaces, a core dielectric layer, a first and a second copper foil layers and containing cavities is provided. An adhesive layer is formed on inner walls of the containing cavities. The first and the second bases are laminated so that the metal bumps are disposed inside the containing cavities. A first base is removed. Blind via holes extending from the upper surface to the metal bumps are formed. A conductive material layer is formed on the first and the second copper foil layers, wherein the conductive material layer fills the blind via holes so as to define conductive through via holes. The conductive material layer is patterned to form a first and a second patterned metal layers.
Public/Granted literature
- US20160230286A1 PACKAGE SUBSTRATE AND MANUFACTURING METHOD THEREOF Public/Granted day:2016-08-11
Information query
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