Invention Grant
US09459648B2 AC coupled single-ended LVDS receiving circuit comprising low-pass filter and voltage regulator
有权
交流耦合单端LVDS接收电路，包括低通滤波器和电压调节器
- Patent Title: AC coupled single-ended LVDS receiving circuit comprising low-pass filter and voltage regulator
- Patent Title (中): 交流耦合单端LVDS接收电路，包括低通滤波器和电压调节器
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Application No.: US13814485Application Date: 2011-08-05
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Publication No.: US09459648B2Publication Date: 2016-10-04
- Inventor: Hiroki Kanamaru
- Applicant: Hiroki Kanamaru
- Applicant Address: LU Luxembourg
- Assignee: GVBB HOLDINGS S.A.R.L.
- Current Assignee: GVBB HOLDINGS S.A.R.L.
- Current Assignee Address: LU Luxembourg
- Agency: Arent Fox LLP
- Priority: JP2010-176236 20100805
- International Application: PCT/JP2011/004474 WO 20110805
- International Announcement: WO2012/017691 WO 20120209
- Main IPC: G05F1/67
- IPC: G05F1/67 ; G05F5/00 ; H04L25/02
Abstract:
A receiving circuit is provided that can accurately detect a clock signal that has a single phase and a small amplitude. A receiving circuit includes an AC coupled circuit 22 that creates an AC coupling between a first end and a second end, a low-pass filter circuit 23, 25 that produces a third signal by applying a low-pass filtering on a second signal that is produced on the second end in response to a first signal that is applied to the first end, and a comparator 21 that inputs the second signal and the third signal.
Public/Granted literature
- US20130229165A1 AC COUPLED SINGLE-ENDED LVDS RECEIVING CIRCUIT COMPRISING LOW-PASS FILTER AND VOLTAGE REGULATOR Public/Granted day:2013-09-05
Information query
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