Invention Grant
- Patent Title: Bus interface optimization by selecting bit-lanes having best performance margins
-
Application No.: US14299319Application Date: 2014-06-09
-
Publication No.: US09459982B2Publication Date: 2016-10-04
- Inventor: Daniel Mark Dreps , Frank D. Ferraiolo , Anand Haridass , Prasanna Jayaraman
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Mitch Harris, Atty at Law, LLC
- Agent Andrew M. Harris; Steven L. Bennett
- Main IPC: G06F11/30
- IPC: G06F11/30 ; G06F11/24 ; G06F11/34 ; G06F11/22 ; G06F11/20

Abstract:
A bus interface selects bit-lanes to allocate as spares by testing the performance margins of individual bit-lanes during initialization or calibration of the bus interface. The performance margins of the individual bit-lanes are evaluated as the operating frequency of the interface is increased until a number of remaining bit-lanes that meet specified performance margins is equal to the required width of the interface. The bit-lanes that do not meet the required performance margins are allocated as spares and the interface can be operated at the highest evaluated operating frequency. When an operating bit-lane fails, one of the spare bit-lanes is allocated as a replacement bit-lane and the interface operating frequency is reduced to a frequency at which the new set of operating bit-lanes meets the performance margins. The operating frequency of the interface can be dynamically increased and decreased during operation and the performance margins evaluated to optimize performance.
Public/Granted literature
- US20150193316A1 BUS INTERFACE OPTIMIZATION BY SELECTING BIT-LANES HAVING BEST PERFORMANCE MARGINS Public/Granted day:2015-07-09
Information query