Invention Grant
US09461627B2 Gate-drive-on-array circuit for use with oxide semiconductor thin-film transistors
有权
用于氧化物半导体薄膜晶体管的栅极驱动阵列电路
- Patent Title: Gate-drive-on-array circuit for use with oxide semiconductor thin-film transistors
- Patent Title (中): 用于氧化物半导体薄膜晶体管的栅极驱动阵列电路
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Application No.: US14424147Application Date: 2014-11-05
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Publication No.: US09461627B2Publication Date: 2016-10-04
- Inventor: Chao Dai
- Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd.
- Applicant Address: CN Shenzhen, Guangdong
- Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
- Current Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
- Current Assignee Address: CN Shenzhen, Guangdong
- Agent Andrew C. Cheng
- Priority: CN201410568872 20141022
- International Application: PCT/CN2014/090286 WO 20141105
- International Announcement: WO2016/061851 WO 20160428
- Main IPC: H03K17/10
- IPC: H03K17/10 ; H03K3/012 ; H01L29/786 ; G09G3/36

Abstract:
A gate-drive-on-array circuit for use with oxide semiconductor thin-film transistors of the present invention uses two constant-voltage negative potential sources (VSS1, VSS2) that are reduced step by step and low potentials of a high-frequency clock signal (CK(n)) and a low-frequency clock signal (LC1, LC2) to ensure an up-pull circuit portion (200) is maintained in a well closed condition during a non-operating period without being affected by the high-frequency clock signal (CK(n)) so as to ensure the circuit operates normally. Further, the first down-pull circuit portion (400) is re-designed to prevent influence thereof imposed on the outputs of the first node (Q(N)) and the output terminal (G(N)) so as to ensure the first node (Q(N)) and the output terminal (G(N)) can supply the outputs normally without generating signal distortion.
Public/Granted literature
- US20160248402A1 GATE-DRIVE-ON-ARRAY CIRCUIT FOR USE WITH OXIDE SEMICONDUCTOR THIN-FILM TRANSISTORS Public/Granted day:2016-08-25
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