Invention Grant
US09461930B2 Modifying data streams without reordering in a multi-thread, multi-flow network processor
有权
在多线程多流网络处理器中修改数据流而无需重新排序
- Patent Title: Modifying data streams without reordering in a multi-thread, multi-flow network processor
- Patent Title (中): 在多线程多流网络处理器中修改数据流而无需重新排序
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Application No.: US13687958Application Date: 2012-11-28
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Publication No.: US09461930B2Publication Date: 2016-10-04
- Inventor: Steven J. Pollock , Deepak Mital , James T. Clee
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Nicholson De Vos Webster & Elliott LLP
- Main IPC: G06F7/00
- IPC: G06F7/00 ; G06F15/00 ; G06F9/455 ; G06F9/46 ; H04L12/863 ; H04L12/933 ; G06F15/167 ; H04L12/931 ; H04L12/851

Abstract:
Described embodiments classify packets received by a network processor. A processing module of the network processor generates tasks corresponding to each received packet. A scheduler generates contexts corresponding to tasks received by the packet classification processor from corresponding processing modules, each context corresponding to a given flow, and stores each context in a corresponding per-flow first-in, first-out buffer of the scheduler. A packet modifier generates a modified packet based on threads of instructions, each thread of instructions corresponding to a context received from the scheduler. The modified packet is generated before queuing the packet for transmission as an output packet of the network processor, and the packet modifier processes instructions for generating the modified packet in the order in which the contexts were generated for each flow, without head-of-line blocking between flows. The modified packets are queued for transmission as an output packet of the network processor.
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