Invention Grant
- Patent Title: Test structure and method of testing electrical characteristics of through vias
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Application No.: US14673400Application Date: 2015-03-30
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Publication No.: US09462692B2Publication Date: 2016-10-04
- Inventor: Shang-Yun Hou , Wei-Cheng Wu , Hsien-Pin Hu , Jung Cheng Ko , Shin-Puu Jeng , Chen-Hua Yu , Kim Hong Chen
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L29/40
- IPC: H01L29/40 ; H05K1/11 ; H01L21/66 ; H05K1/02 ; H01L21/768 ; H01L23/00

Abstract:
A method and apparatus for testing the electrical characteristics, such as electrical continuity, is provided. A substrate, such as a wafer or an interposer, having a plurality of through vias (TVs) is provided. Along one side of the substrate, a conductive layer electrically couples two or more of the TVs. Thereafter, the electrical characteristics of the TVs may be test by, for example, a probe card in electrical contact with the TVs on the other side of the substrate. During testing, current passes through a first TV from a first side of the substrate, to the conductive layer on a second side of the substrate, to a second TV, and back to the first side of the substrate through the second TV.
Public/Granted literature
- US20150208504A1 Test Structure and Method of Testing Electrical Characteristics of Through Vias Public/Granted day:2015-07-23
Information query
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