Semiconductor devices are provided. One of the semiconductor devices may include a synthetic clock generator and a flag signal generator. The synthetic clock generator may be configured to generate a synthetic clock signal in response to a test enablement signal. The synthetic clock signal may be generated from a clock signal to include a first section pulse and a second section pulse having different pulse widths. The flag signal generator may be configured to latch a test signal in response to the synthetic clock signal to generate a flag signal.