Invention Grant
- Patent Title: Localized region of isolated silicon over recessed dielectric layer
- Patent Title (中): 隔离硅的局部区域在凹陷介电层上
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Application No.: US14301765Application Date: 2014-06-11
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Publication No.: US09466520B2Publication Date: 2016-10-11
- Inventor: Daniel Nelson Carothers , Jeffrey R. Debord
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent John R. Pessetto; Frank D. Cimino
- Main IPC: H01L21/762
- IPC: H01L21/762 ; H01L21/306 ; H01L21/02 ; H01L21/3105 ; H01L21/84

Abstract:
An integrated circuit is formed by forming an isolation recess in a single crystal substrate which includes silicon, filling the isolation recess with isolation dielectric material, and planarizing the isolation dielectric material to be coplanar with the top surface of the substrate to form a buried isolation layer. A non-selective epitaxial process forms single-crystalline silicon-based semiconductor material on exposed areas of the substrate and polycrystalline or amorphous silicon-based material on the buried isolation layer. A cap layer is formed over the epitaxial silicon-based material, and a radiantly-induced recrystallization process causes the polycrystalline or amorphous silicon-based material to form single-crystalline semiconductor over the buried isolation layer.
Public/Granted literature
- US20150294901A1 LOCALIZED REGION OF ISOLATED SILICON OVER RECESSED DIELECTRIC LAYER Public/Granted day:2015-10-15
Information query
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