Invention Grant
US09466577B2 Semiconductor interconnect structure with stacked vias separated by signal line and method therefor
有权
具有通过信号线分离的堆叠通孔的半导体互连结构及其方法
- Patent Title: Semiconductor interconnect structure with stacked vias separated by signal line and method therefor
- Patent Title (中): 具有通过信号线分离的堆叠通孔的半导体互连结构及其方法
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Application No.: US12035843Application Date: 2008-02-22
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Publication No.: US09466577B2Publication Date: 2016-10-11
- Inventor: Yaojian Lin
- Applicant: Yaojian Lin
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins and Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L23/00
- IPC: H01L23/00
Abstract:
A semiconductor device is made by forming a first conductive layer over a substrate, forming a first passivation layer over the first conductive layer, forming a first via in the first passivation layer to expose the first conductive layer, forming a second conductive layer over the first passivation layer and within the first via to electrically connect to the first conductive layer, forming a second passivation layer over the second conductive layer, and forming a second via in the second passivation layer to expose the second conductive layer. The second via is smaller than the first via. The second via is either physically separate from or disposed over the first via. The second conductive layer within the second via has a flat surface which is wider than the second via. An under bump metallization is formed in the second via and electrically connected to the second conductive layer.
Public/Granted literature
- US20090212441A1 Semiconductor Interconnect Structure with Stacked Vias Separated by Signal Line and Method Therefor Public/Granted day:2009-08-27
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