Invention Grant
- Patent Title: Geometry of MOS device with low on-resistance
- Patent Title (中): 具有低导通电阻的MOS器件的几何
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Application No.: US11964696Application Date: 2007-12-26
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Publication No.: US09466596B2Publication Date: 2016-10-11
- Inventor: Sehat Sutardja , Ravishanker Krishnamoorthy
- Applicant: Sehat Sutardja , Ravishanker Krishnamoorthy
- Applicant Address: BB St. Michael
- Assignee: Marvell World Trade Ltd.
- Current Assignee: Marvell World Trade Ltd.
- Current Assignee Address: BB St. Michael
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L27/02 ; H01L21/8234 ; H01L27/088 ; H01L29/06 ; H01L29/423 ; H01L29/78 ; H01L29/417
Abstract:
A Metal Oxide Semiconductor (MOS) device formed on a substrate and a method for forming the MOS device. The MOS device includes a drain region, a gate region surrounding the drain region, source regions arranged around the gate region and across from the drain region, and bulk regions arranged around the gate region and separating the source regions. The gate region is formed in a loop around the drain region. In this manner, the on-resistance (Ron) of a MOS device is decreased without also increasing the area of the MOS device.
Public/Granted literature
- US20080157195A1 GEOMETRY OF MOS DEVICE WITH LOW ON-RESISTANCE Public/Granted day:2008-07-03
Information query
IPC分类:
