Invention Grant
- Patent Title: Non-floating vertical transistor structure
- Patent Title (中): 非浮动垂直晶体管结构
-
Application No.: US14702771Application Date: 2015-05-04
-
Publication No.: US09466713B2Publication Date: 2016-10-11
- Inventor: Tzung-Han Lee
- Applicant: INOTERA MEMORIES, INC.
- Applicant Address: TW Taoyuan
- Assignee: INOTERA MEMORIES, INC.
- Current Assignee: INOTERA MEMORIES, INC.
- Current Assignee Address: TW Taoyuan
- Agent Winston Hsu; Scott Margo
- Priority: TW103133369A 20140925
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/66 ; H01L29/08 ; H01L21/265 ; H01L21/324 ; H01L21/225 ; H01L21/266 ; H01L27/108 ; H01L21/8234

Abstract:
A non-floating vertical transistor includes a substrate and a protuberant structure extending from the substrate. A segregating pillar is inside the protuberant structure. A pair of segregated bit-lines which are segregated by the segregating pillar is disposed in the substrate and in the protuberant structure and adjacent to the bottom of the segregating pillar. A gate oxide layer is attached to the sidewall of the protuberant structure. A word-line is adjacent to the gate oxide layer so that the gate oxide layer is sandwiched between the word-line and a doped deposition layer.
Public/Granted literature
- US20160093732A1 NON-FLOATING VERTICAL TRANSISTOR STRUCTURE Public/Granted day:2016-03-31
Information query
IPC分类: