An integrated circuit counter includes a cascaded chain of bit counters, which are collectively configured to count a number of first edges of a counter input signal received at an input thereof and output the count as a counter output signal. The cascaded chain includes at least two bit counters, which are: (i) configured to support both counter and buffer modes of operation, and (ii) responsive to respective bypass control bit signals having values that specify whether a corresponding one of the at least two bit counters is disposed in the counter or buffer mode of operation.