Invention Grant
- Patent Title: Method for displaying timing information of an integrated circuit floorplan in real time
- Patent Title (中): 实时显示集成电路平面布置图的定时信息的方法
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Application No.: US14523176Application Date: 2014-10-24
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Publication No.: US09471742B2Publication Date: 2016-10-18
- Inventor: Yi-Lin Chuang , Huang-Yu Chen , Yun-Han Lee
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A method includes (a) generating timing information of an integrated circuit (IC) floorplan by a processing unit, (b) displaying on a display device a representation of the IC floorplan according to the timing information, (c) receiving user input via an input device, the user input associated with an IC macro of the IC floorplan, (d) updating the timing information associated with the IC macro to generated updated timing information according to the user input, and (e) altering display of the representation according to the updated timing information.
Public/Granted literature
- US20150046890A1 Method for Displaying Timing Information of an Integrated Circuit Floorplan Public/Granted day:2015-02-12
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