Invention Grant
- Patent Title: Apparatuses and methods for improving retention performance of hierarchical digit lines
- Patent Title (中): 提高分级数字线路保持性能的装置和方法
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Application No.: US13843209Application Date: 2013-03-15
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Publication No.: US09472252B2Publication Date: 2016-10-18
- Inventor: Ryan Hofstetter , Adam El-Mansouri
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dorsey & Whitney LLP
- Main IPC: G11C5/06
- IPC: G11C5/06 ; G11C7/18
Abstract:
Apparatuses and methods for improving retention performance of hierarchical digit lines are disclosed herein. An example apparatus may include a first digit line portion and a second digit line portion. The apparatus may further include a first selector configured to selectively couple the first digit line portion to the second digit line portion based, at least in part, on a first control signal. The apparatus may further include a second selector configured to selectively couple the second digit line portion to a voltage based, at least in part, on a second control signal.
Public/Granted literature
- US20140268974A1 APPARATUSES AND METHODS FOR IMPROVING RETENTION PERFORMANCE OF HIERARCHICAL DIGIT LINES Public/Granted day:2014-09-18
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