Invention Grant
US09472255B2 Semiconductor device including a clock generating circuit for generating an internal signal having a coarse delay line, a fine delay line and a selector circuit
有权
半导体器件包括用于产生具有粗延迟线的内部信号的时钟发生电路，精细延迟线和选择器电路
- Patent Title: Semiconductor device including a clock generating circuit for generating an internal signal having a coarse delay line, a fine delay line and a selector circuit
- Patent Title (中): 半导体器件包括用于产生具有粗延迟线的内部信号的时钟发生电路，精细延迟线和选择器电路
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Application No.: US14193345Application Date: 2014-02-28
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Publication No.: US09472255B2Publication Date: 2016-10-18
- Inventor: Katsuhiro Kitagawa
- Applicant: PS4 LUXCO S.A.R.L.
- Applicant Address: LU Luxembourg
- Assignee: PS4 Luxco S.a.r.l.
- Current Assignee: PS4 Luxco S.a.r.l.
- Current Assignee Address: LU Luxembourg
- Agency: Stoel Rives LLP
- Priority: JP2009-062882 20090316
- Main IPC: G06F1/00
- IPC: G06F1/00 ; G11C7/22 ; G11C5/06 ; G11C7/10 ; H03L7/081 ; H03L7/087
Abstract:
A semiconductor device includes a data input/output circuit that has an ODT function and a DLL circuit that generates an internal clock for determining an operation timing of the data input/output circuit. The DLL circuit has a first mode for controlling a phase of the internal clock in a precise manner and a second mode for operating with low power consumption. When the data input/output circuit does not perform an ODT operation, the DLL circuit operates in the first mode, and when the data input/output circuit performs the ODT operation, the DLL circuit operates in the second mode. In this manner, the operation mode of the DLL circuit is switched over depending on the ODT operation, so that the power consumption in the ODT operation in which strict phase control is not required can be reduced.
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