A static random access memory includes a first inverter and a second inverter, a first n-type metal-oxide-semiconductor (NMOS) transistor, and a second NMOS transistor. An output terminal of the first inverter is connected to an input terminal of the second inverter, and an input terminal of the first inverter is connected to an output terminal of the second inverter. The first NMOS transistor is configured to control a write signal, and the second NMOS transistor is configured to control a read signal. The first NMOS transistor is connected to the input terminal of the first inverter, the output terminal of the second inverter, a write word line, and a write bit line. The second NMOS transistor is connected to the output terminal of the first inverter, the input terminal of the second inverter, a read word line, and an internal line.