Invention Grant
- Patent Title: Nonvolatile semiconductor memory device
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Application No.: US14677111Application Date: 2015-04-02
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Publication No.: US09472295B2Publication Date: 2016-10-18
- Inventor: Yasuhiro Shiino , Eietsu Takahashi , Koki Ueno
- Applicant: KABUSHIKI KAISHA TOSHIBA
- Applicant Address: JP Minato-ku
- Assignee: KABUSHIKI KAISHA TOSHIBA
- Current Assignee: KABUSHIKI KAISHA TOSHIBA
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2011-084762 20110406
- Main IPC: G11C16/04
- IPC: G11C16/04 ; G11C16/26 ; G11C11/56 ; G11C16/34

Abstract:
A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.
Public/Granted literature
- US20150213903A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2015-07-30
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