Invention Grant
- Patent Title: Interconnect arrangement with stress-reducing structure and method of fabricating the same
- Patent Title (中): 具有应力降低结构的互连装置及其制造方法
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Application No.: US14987429Application Date: 2016-01-04
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Publication No.: US09472508B2Publication Date: 2016-10-18
- Inventor: Yi-Ruei Lin , Yen-Ming Peng , Han-Wei Yang , Chen-Chung Lai
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Birch, Stewart, Kolasch & Birch, LLP
- Main IPC: H01L23/58
- IPC: H01L23/58 ; H01L23/00 ; H01L23/48 ; H01L21/768 ; H01L23/31 ; H01L23/532
Abstract:
A semiconductor device structure and a method of fabricating the same are provided. The semiconductor structure includes a substrate and an interconnection structure formed over the substrate. The interconnection structure includes a first dielectric layer and a first stress-reducing structure formed in the first dielectric layer. The interconnection structure further includes a first conductive feature formed in the first dielectric layer, and the first conductive feature is surrounded by the first stress-reducing structure.
Public/Granted literature
- US20160118350A1 INTERCONNECT ARRANGEMENT WITH STRESS-REDUCING STRUCTURE AND METHOD OF FABRICATING THE SAME Public/Granted day:2016-04-28
Information query
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